1. Field of the Invention
This invention generally relates to methods and systems for pattern suppression in logic for wafer inspection.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Wafer inspection, using either optical or electron beam technologies, is an important technique for debugging semiconductor manufacturing processes, monitoring process variations, and improving production yield in the semiconductor industry. With the ever decreasing scale of modern integrated circuits (ICs) as well as the increasing complexity of the manufacturing process, inspection becomes more and more difficult.
In each processing step performed on a semiconductor wafer, the same circuit pattern is printed in each die on the wafer. Most wafer inspection systems take advantage of this fact and use a relatively simple die-to-die comparison to detect defects on the wafer. However, the printed circuit in each die may include many areas of patterned features that repeat in the x or y direction such as the areas of DRAM, SRAM, or FLASH. This type of area is commonly referred to as an array area (the rest of the areas are called random or logic areas). To achieve better sensitivity, advanced inspection systems employ different strategies for inspecting the array areas and the random or logic areas.
Inspecting the array areas tends to be simpler in some ways than inspecting random or logic areas. For instance, the array areas tend to include repeating, periodic patterned features. Therefore, removing the signals or data corresponding to such patterned features is relatively easy. For example, relatively small cells that have the same repeating patterned features may be compared to each other, signals and data from the patterned features will cancel each other out, and differences detected by such comparisons can be identified as potential defects. Since such cell-to-cell comparisons can be performed within a single die, the comparisons will not be affected by non-local noise sources such as process variations across the wafer. In addition, since patterned features in the array areas tend to repeat periodically across nearly an entirety of the array areas, signals or data corresponding to such patterned features can be removed relatively easily using, for example, Fourier filtering that can be performed optically or during image processing.
Since random or logic areas on wafers do not include such repeating, periodic features, the inspection approaches described above generally cannot be used for such areas. Instead, typically, inspection of random or logic areas is performed by using bright field imaging, in which specularly reflected light from the wafer is detected to form an image of the wafer in which the features in the random or logic areas are resolved. Since the features in such areas tend to not repeat on a regular basis within a die, images such as those described above that have been generated at the same within die position in multiple dies on the wafer are compared. Since the same patterns should be formed at the same within die position in multiple dies on the wafer, any differences detected by such comparisons may be identified as potential defects.
Such inspection of random or logic areas has, therefore, a number of disadvantages that make this inspection more difficult in some ways compared to array area inspection. For instance, bright field type inspection that is typically used for random or logic areas tends to be slower than dark field inspection and the optical requirements for bright field inspection systems tend to make such systems much more expensive than dark field inspection systems (e.g., due to the imaging capability required in such systems). In addition, since such inspection tends to rely on die-to-die comparisons of signals or data for defect detection, such inspection tends to be less sensitive than that achievable for array areas (e.g., due to non-local noise sources such as those described above). Furthermore, since the features formed in random or logic areas are not repeating and periodic in the same way that features formed in array areas are, eliminating the signals or data for non-defective features in random or logic areas is much more difficult than in array areas (e.g., since Fourier filtering is generally not possible).
Due to shrinking design rules as well as increasingly complex fabrication techniques, improvements in the sensitivity of random or logic area inspection will be required to keep pace with the technology. Accordingly, it would be advantageous to develop methods and systems for wafer inspection of random or logic areas that do not have one or more of the disadvantages described above.